12.
The minimum number of NAND gates required to construct an OR gate is
a. 1
b. 2
c. 3
d. 4
The minimum number of NAND gates needed to construct a 2-input OR gate is 3, making option c. 3 correct.
Option Analysis
- a. 1: A single NAND gate outputs
A⋅B̅, which equals 1 unless both inputs are 1, unlike OR (A+B) that outputs 0 only when both are 0. This fails the truth table. Incorrect. - b. 2: Two NAND gates can make AND (NAND + NOT) or NOT, but cannot produce OR’s logic where output is 1 if either input is 1. Insufficient for De Morgan transformation. Incorrect.
- c. 3: Correct. Use De Morgan:
A+B=A̅⋅B̅̅. First two NANDs invert inputs (A̅=A NAND A,B̅=B NAND B); third NANDs their outputs to get OR. Verified by truth table simulation. - d. 4: Possible but not minimum; extra inverter wastes a gate. Standard digital logic uses 3. Incorrect.
Circuit Explanation
NAND is universal as it implements NOT, AND, OR via combinations.
A ─┬─ NAND ─ A̅
│
└──────────┐
B ─┬─ NAND ─ B̅ │
│ │
└───────────────┼─ NAND ─ Y = A + B
│
│
└──────────┐
B ─┬─ NAND ─ B̅ │
│ │
└───────────────┼─ NAND ─ Y = A + B
│
This matches OR truth table: 00→0, 01→1, 10→1, 11→1.
Why NAND is Universal
NAND implements NOT (tied inputs), AND (NAND + NOT), OR via A̅⋅B̅̅. This saves components in VLSI.
Step-by-Step OR Implementation
- Invert A and B using two NANDs (both inputs tied).
- NAND the inverses for final OR output.
- 3 gates total; fewer impossible per Boolean minimization.
Exam Relevance
Common in GATE, CSIR NET; distinguishes 3 vs. 4-gate misconceptions. Practice verifies via simulation.
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